C4 (Controlled-Collapse Chip Connection) is used to connect IC (integrated circuit) chips to substrates in electronic packages. Moreover, C4 is a flip-chip technology in which the interconnections may be provided using relatively small solder balls on the chip surface. Because it is an area array, C4 technology may provide relatively high densities for chip interconnections.
C4 technology has been used since the 1960s and has proven reliable in the semiconductor field. Historically, PbSn (lead-tin) solder has been evaporated through a metal mask. In the 1990s, electrochemical fabrication of C4 interconnections was introduced. See, for example, M. Datta, et al., “Electrochemical Fabrication of Mechanically Robust PbSn Interconnections”, J. Electrochem. Soc., 142, 3779 (1995), U.S. Pat. No. 5,162,257 to Yung, and WO 96/30933, the disclosures of which are hereby incorporated herein in their entirety by reference. Electroplating may be more extendible than evaporation to small C4-pad dimensions, and may provide closer pad spacing, larger wafers, and/or lower-melting solders (having a higher content of Sn).
U.S. Pat. No. 5,937,320 discusses barrier layers for electroplated PbSn eutectic solder joints. An electrochemically fabricated C4 interconnection may have a barrier layer between the electroplated tin-rich solder bump and the ball-limiting metallurgy that protects the terminal metal in the ball-limiting metallurgy from attack by the Sn in the solder. The barrier layer may be electroplated through the same photoresist mask as the solder and thus may not require a separate patterning step. A thin layer of electroplated nickel may serve as a reliable barrier layer between a copper-based ball-limiting metallurgy and a tin-lead (PbSn) eutectic C4 ball. U.S. Pat. No. 6,622,907 discusses a sacrificial seed layer process for forming C4 solder balls. The disclosures of U.S. Pat. Nos. 5,937,320 and 6,622,907 are hereby incorporated herein in their entirety by reference.